1. Field
Exemplary embodiments of the present invention relate to a data transmission circuit for operating a memory at high speed, a memory including the same, and a data transmission method.
2. Description of the Related Art
A nonvolatile memory is a memory device which maintains data stored therein even though power supply is cut off. As the threshold voltage of a memory cell may change based on the amount of charges stored in a conduction band of a floating gate, data is stored in the nonvolatile memory using the characteristics.
When a program pulse is applied to the floating gate, the threshold voltage of the memory cell increases. Depending on the value of data to be stored in the memory cell through the program pulse, the threshold voltage of the memory cell is changed. Since a plurality of memory cells within the nonvolatile memory have different characteristics, the threshold voltages of memory cells storing the same data do not have one value, but form a predetermined distribution.
Meanwhile, a plurality of memory cells in the nonvolatile memory are connected to corresponding bit lines. Each of the bit lines is coupled to a corresponding page buffer. The page buffer drives the bit line to a predetermined voltage level, senses the voltage of the bit line, and store or output the sensed value, in order to perform a specific operation such as a read or write operation for a selected memory cell. The page buffer includes one or more latches configured to perform an operation of storing data inputted from outside and driving a bit line to a predetermined voltage, or an operation of sensing the voltage of the bit line to store data corresponding to the voltage of the bit line and transferring the stored voltage to the outside.
Among the latches included in the page buffer, a cache latch serves to store data of a selected memory cell during a data read operation, and to drive a line for transferring data to the outside depending on the stored data. Hereafter, referring to FIG. 1, how the data stored in the cache latch of the page buffer is transferred to the outside of the page buffer will be described.
FIG. 1 is a diagram illustrating a part of a conventional memory, in order to describe a process in which data of a cache latch is transferred in the conventional memory.
Referring to FIG. 1, the memory includes a plurality of page buffer groups PG0 to PGN, a plurality of data transmission lines IO_0/IO_0B to IO_N/IO_NB, and an output line OUT/OUTB. Each of the page buffer groups PG0 to PGN includes one or more page buffers PB0 to PBM. The plurality of data transmission lines IO_0/IO_0B to IO_N/IO_NB correspond to the respective page buffer groups PG0 to PGN and are configured to transfer data of a selected page buffer among page buffers PB0 to PBM included in each of the page buffer groups PG0 to PGN. The output line OUT/OUTB is configured to transfer data of a selected transmission line among the plurality of data transmission lines IO_0B/IO_0B to IO_N/IO_NB. Each of the page buffers includes a cache latch LAT.
Referring to FIG. 1, an operation of outputting data of a selected page buffer will be described. The memory transfers differential data through the data transmission lines IO_0 to IO_N and OUT to transfer data and the complementary data transmission lines IO_0B to IO_NB and OUTB to transfer complementary data.
The page buffers PB0 to PBM included in one page buffer group are connected to the data transmission lines IO_0/IO_0B to IO_N/IO_NB corresponding to the respective page buffer groups through the respective switches SWB0 to SWBM. Furthermore, the data transmission lines corresponding to the respective page buffer groups are connected to the output line OUT/OUTB through the respective switches SWG0 to SWGN.
During a read operation, a page buffer group including a page buffer having data to be read is selected, and a switch corresponding to the selected page buffer group is turned on to electrically connect a data transmission line corresponding to the selected page buffer group to the output line OUT/OUTB. Furthermore, the page buffer having data to be read is selected, and a switch connected to the selected page buffer is turned on to electrically connect the selected page buffer to the data transmission line. Here, selection signals SEL_PB0<0:M> to SEL_PBM<0:N> to select the respective page buffers PB0 to PBM and selection signals SEL_PG<0:N> to select the respective page buffer groups PG0 to PGN may be generated by decoding an address (not illustrated in FIG. 1) inputted to the memory.
For example, it is supposed that data of the first page buffer PB0 of the first page buffer group PG0 is read. The selection signal SEL_PG<0> is activated to select the first page buffer group PG0, and the selection signal SEL_PB0<0> is activated to select one page buffer among the page buffers PB0 to PBM included in the first page buffer group PG0. When the page buffer group PG0 and the page buffer PB0 included in the page buffer group PG0 are selected, the switch SWG0 is turned on in response to the selection signal SEL_PG<0>, and the switch SWB0 is turned on in response to the selection signal SEL_PB0<0>. Therefore, the cache latch LAT included in the page buffer PB0 of the page group PG0 is electrically connected to the output line OUT/OUTB.
In order for the output line OUT/OUTB to receive data included in the cache latch LAT, the output line OUT/OUTB is precharged to a precharge voltage before the data read operation is started. When the cache latch LAT and the output line OUT/OUTB are electrically connected to each other during the read operation, the output line OUT/OUTB is driven to a predetermined voltage by the cache latch LAT.
Here, the number of page buffer groups connected to one output line OUT/OUTB and the number of page buffers included in one page buffer group approaches several tens to hundreds. Therefore, the loading of the output line OUT/OUTB is significantly large. However, since the output line OUT/OUTB is driven only by the cache latch LAT, it takes a considerably long time to drive the voltage of the output line OUT/OUTB to a voltage corresponding to data which is to be outputted. When it takes a considerably long time to drive the output line OUT/OUTB, it means that the memory has difficulties in operating at high speed.